Phase locked loop (PLL) circuits are widely known and used in computers, radios, telecommunications and many other electronic applications. One of the common uses of a PLL is to synthesize new frequencies ranging from a fraction of Hertz (Hz) up to many gigahertz (GHz), which are a multiple of a reference frequency and are as stable as reference frequency. Typical analog PLLs include a phase and frequency detector (PFD), a charge pump, a loop filter, a current controlled or voltage controlled oscillator (VCO) and a feedback path with a divider. A PLL uses negative feedback to control the output frequency of the oscillator until it matches with the reference signal in both frequency and phase. A fully digital PLL uses a digitally controlled oscillator (DCO), which is more robust and flexible than a conventional VCO. Digital PLLs are easy to design and less sensitive to voltage noise as compared to analog PLLs.
FIG. 1 illustrates a prior art digital phase lock loop (DPLL) circuit 100.
As illustrated in FIG. 1, DPLL circuit 100 includes a phase and frequency detector (PFD) 102, a time to digital convertor (T2D) 104, a digital loop filter 106, a digitally controlled oscillator (DCO) 108, a feedback divider 110 and a synchronizing flip-flop (sync FF) 112. In this illustration, each of PFD 102, T2D 104, digital loop filter 106, DCO 108, feedback divider 110 and sync FF 112 are illustrated as distinct devices. However, at least one of PFD 102, T2D 104, digital loop filter 106, DCO 108, feedback divider 110 and sync FF 112 may be combined as a unitary device.
PFD 102 is arranged to receive a reference clock signal 114 and a feedback clock signal 126 and to output a phase difference pulse 116. T2D 104 is arranged to output a digital word 118 based on phase difference pulse 116. In one example, T2D is arranged to receive phase difference pulse 116 directly from PFD 102. Alternatively, intermediate circuitry may be included to modify phase difference pulse 116 prior to T2D 104. Non-limiting examples of intermediate circuitry include matching networks, amplifiers, filters, resistors, etc.
Digital loop filter 106 is arranged to output a filtered signal 120 based on digital word 118. In one example, digital loop filter 106 is arranged to receive digital word 118 directly from T2D 104. Alternatively, intermediate circuitry may be included to modify digital word 118 prior to digital loop filter 106.
DCO 108 is arranged to output an oscillator clock signal 122 based on filtered signal 120. In one example, DCO 108 is arranged to receive filtered signal 120 directly from digital loop filter 106. Alternatively, intermediate circuitry may be included to modify filtered signal 120 prior to DCO 108.
Feedback divider 110 is arranged to output a divided clock signal 124 based on oscillator clock signal 122. In one example, feedback divider 110 is arranged to receive oscillator clock signal 122 directly from DCO 108 and to output a divided clock signal 124. Alternatively, intermediate circuitry may be included to modify oscillator clock signal 122 prior to feedback divider 110.
Sync FF 112 is arranged to output feedback clock signal 126 by synchronizing divided clock signal 124 with oscillator clock signal 122. In one example, sync FF 112 is arranged to receive divided clock signal 124 directly from feedback divider 110 and to receive oscillator clock signal 122 directly from DCO 108. Alternatively, intermediate circuitry may be included to modify at least one of divided clock signal 124 and oscillator clock signal 122 prior to sync FF 112.
In a conventional DPLL circuit as shown in prior art FIG. 1, reference clock signal 114 is low frequency clock typically in the order of MHz and oscillator clock signal 122 is high frequency clock in the order of GHz. Reference clock signal 114 may be from an external crystal oscillator with a stable frequency. Oscillator clock signal 122 is divided by feedback divider 110 to generate feedback clock signal 126 so that the frequency of feedback clock signal 126 is closer to the order of the frequency of reference clock signal 114. After going through feedback divider 110, reference clock signal 114 and feedback clock signal 126 should line up so that the frequency of oscillator clock signal 122 is a multiple of reference clock signal 114. However, feedback divider 110 introduces noise. Sync FF 112 synchronizes divided clock signal 124 with oscillator clock signal 122 to address this noise by cleaning up the edges of divided clock signal 124.
PFD 102 generates phase difference pulse 116, which is proportional to the phase difference between reference clock signal 114 and feedback clock signal 126. The time duration of phase difference pulse 116 is converted to digital word 118 by T2D 104, which indicates the phase or frequency error between the two clock signals.
Digital loop filter 106 may be a low pass filter, which may operate to eliminate high frequency components of digital word 118 and pass the low frequencies to DCO 108.
DCO 108 may be any known DCO, a non-limiting example of which includes a combination of digital and analog circuits like a digital to analog converter (DAC) and a voltage controlled oscillator (VCO). Other alternate implementations may include current source or fixed capacitor DCOs.
Feedback divider 110 divides oscillator clock signal 122 by an integer number (M) so that divided clock signal 124 matches in frequency and phase with reference clock signal 114. Integer number M may be programmable in most cases, when there is a need to change the output frequency for different applications. Feedback divider 110 and sync FF 112 receive oscillator clock signal 122. Operation of feedback divider 110, and sync FF 112 consumes large amounts of power, even more than the remaining portions of DPLL circuit 100 combined.
FIG. 2 illustrates conventional PFD 102 for DPLL circuit 100 of FIG. 1.
As illustrated in FIG. 2, PFD 102 includes a flip-flop 202, a flip-flop 204 and an AND gate 206.
Flip-flop 202 is arranged to receive an input VDD 208 on its D input, reference clock signal 114 on its C input, and a reset signal 216 on its CLR input and to output an UP signal 212 on its Q output.
Flip-flop 204 is arranged to receive an input VDD 210 on its D input, feedback clock signal 126 on its C input, and reset signal 216 on its CLR input and to output a DOWN signal 214 on its Q output.
AND gate 206 is arranged to receive UP signal 212 and DOWN signal 214 and to output reset signal 216.
PFD 102 compares the phase and frequency of reference clock signal 114 with feedback clock signal 126 in order to eventually lock the two clocks. UP signal 212 and DOWN signal 214 provided by PFD 102 in FIG. 2 represent phase difference pulse 116 of DPLL circuit 100 of FIG. 1.
The “D” inputs of flip-flop 202 and flip-flop 204 are tied to “VDD”. When reference clock signal 114 goes high, PFD 102 expects feedback clock signal 126 to be there and rises UP signal 212. When feedback clock signal 126 goes high it makes DOWN signal 214 go high. With UP signal 212 and DOWN signal 214 both high, reset signal 216, an output of AND gate 206 becomes high resetting both flip-flop 202 and flip-flop 204. This in turn terminates both UP signal 212 and DOWN signal 214. UP signal 212 and DOWN signal 214 eventually become zero as reference clock signal 114 and feedback clock signal 126 line up. The relationship between different signals will now be further described with reference to FIG. 3.
FIG. 3 illustrates timing diagram waveforms for the various signals of DPLL circuit 100.
FIG. 3 includes a waveform 302 for oscillator clock signal 122, a waveform 304 for feedback clock signal 126, a waveform 306 for reference clock signal 114, a waveform 308 for DOWN signal 214, a waveform 310 for UP signal 212 and a timeline 312. Here, UP signal 212 and DOWN signal 214 correspond to phase difference pulse 116 from PFD 102. As opposed to showing a single, three-state waveform (a positive HIGH state, a negative HIGH state and a zero state), phase difference pulse 116 is shown as two separate signals, UP signal 212 having a positive HIGH state and a zero state and DOWN signal 214 having a positive HIGH state and a zero state.
Waveform 302 includes clock cycles 313, 315 and 317. Waveform 304 includes a clock cycle 320. Waveform 306 includes a clock cycle 328. Waveform 308 includes pulses 338 and 340. Waveform 310 includes a pulse 346.
As seen in waveform 302, frequency of oscillator clock signal 122 varies based on the phase error between reference clock signal 114 and feedback clock signal 126. Comparing oscillator waveform 304 with waveform 302, it is clear that feedback clock signal 126 goes high once every M cycles of oscillator clock signal 122. Reference clock signal 114 is a master clock signal received by DPLL circuit 100.
As illustrated with waveform 304, waveform 302 and waveform 308, a rising edge 314 of feedback clock signal 126 in the absence of a rising edge of reference clock signal 114 results in DOWN signal 214 transitioning to logic high at a rising edge 330. Conversely, a subsequent occurrence of a rising edge 322 of reference clock signal 114 results in a transition of DOWN signal 214 to logic low at a falling edge 332. The width of pulse 338 of waveform 308 represents how much reference clock signal 114 is lagging feedback clock signal 126.
As illustrated with waveform 304, waveform 306 and waveform 310, a rising edge 324 of reference clock signal 114 in the absence of a rising edge of feedback clock signal 126 results in UP signal 212 transitioning to logic high at a rising edge 342. Conversely, a subsequent occurrence of a rising edge 316 of feedback clock signal 126 results in a transition of UP signal 212 to logic low at a falling edge 344. The width of pulse 346 of waveform 310 represents by how much reference clock signal 114 is leading feedback clock signal 126.
In this example prior art, pulses 338 and 346 represent phase and frequency error between reference clock signal 114 and feedback clock signal 126. When this phase and frequency error is received by DCO 108 via T2D 104 and digital loop filter 106, DCO 108 operates to adjust the frequency of oscillator clock signal 122 provided by DCO 108 so as to match the feedback clock signal 126 with reference clock signal 114 in phase and frequency. Clock cycles 313, 315 and 317 of waveform 302 represent change in the clock period of oscillator clock signal 122 to compensate for phase and frequency error represented by pulses 338, 346 and 340 respectively.
In other words, when phase difference pulse 116 is positive, feedback clock signal 126 lags reference clock signal 114, whereas the width of the pulse in phase difference pulse 116 will indicate how much feedback clock signal 126 lags reference clock signal 114. Similarly, when phase difference pulse 116 is negative, feedback clock signal 126 leads reference clock signal 114, whereas the width of the pulse in phase difference pulse 116 will indicate how much feedback clock signal 126 leads reference clock signal 114. Ideally, phase difference pulse 116 will be zero, (UP signal 212 and DOWN signal 214 will not include any pulses), thus indicating that reference clock signal 114 and feedback clock signal 126 are aligned and oscillator clock signal 122 is locked at a stable frequency.
As discussed above using FIG. 1 through FIG. 3, PFD 102 of conventional DPLL circuit 100 compares feedback clock signal 126 with the reference clock signal 114. However, as discussed above, to generate feedback clock signal 126, DPLL circuit employs feedback divider 110 and sync FF 112. Operation of feedback divider 110 and sync FF 112 consumes lot of power, thus increasing the overall power usage of conventional DPLL circuit 100.
What is needed is a DPLL circuit that will operate with less power than conventional DPLL circuits.